The present invention pertains generally to electronic circuit testing, and more particularly to a method for reducing false electrical rule violations during the testing of a digital circuit design by making use of designer knowledge about signals which are mutually exclusive in the circuit design.
The semiconductor industry continues to yield integrated circuits (ICs) of increasing density in order to reduce their overall required chip space and therefore allow circuit designs of increasing complexity. At the present time, such ICs can implement complex circuit designs with up to millions of transistors.
Due to the sheer volume of transistors and complexity of modern day circuit designs, the testing of such circuit designs prior to actual implementation requires increasingly complex testing tools. These testing tools typically operate on a net list file describing a schematic of the circuit design, which specifies the components, nodes, connections of the components between the nodes, and relative sizes of each of the components. Logic and timing analysis is performed via computer simulations of the circuit design. Given a set of specifications, or electrical rules checks (ERCs), a test will run the analysis and output violations of the specifications.
Present day testing tools are limited to generating specification violations for every violation of the electrical rules checks, without regard to the impossibility of such a violation due to signals in the circuit that are mutually exclusive. Accordingly, xe2x80x9cfalsexe2x80x9d ERC violations are often reported for signal combinations that cannot actually occur. In a large design, this can result in the reporting of a considerably large number of xe2x80x9cfalsexe2x80x9d ERC violations, which get reported to the designers from the testers. Upon investigation, the designers determine that the xe2x80x9cfalsexe2x80x9d ERC violations are not really violations at all because the combination of signals that result in the violation cannot actually occur because the signals are mutually exclusive. Accordingly, it will be appreciated that the reporting of false ERC violations results in loss of both designer and tester time, and is thus undesirable.
Accordingly, a need exists for a way to communicate mutually exclusive signal information to the testing tool to avoid reporting of ERC violations that cannot in fact occur due to mutually exclusive signals.
The present invention is a novel method for reducing the reporting of false ERC violations by a testing tool during the testing of a digital circuit design having mutually exclusive signals. In accordance with the method of the invention, all relevant mutually exclusive signal relationships in the circuit design under test are determined. Then, based on the relevant mutually exclusive signal relationships, all possible permutations of active signals used in the analysis are determined. For each possible permutation, the analysis is performed using the active signals associated with the permutation while ignoring the effect of all signals that are inactive based on the mutually exclusive signal relationships.
In a preferred embodiment, the list of relevant mutually exclusive signal relationships in the circuit design under test is performed by obtaining a list of mutually exclusive signal relationships in the circuit, determining a set of signals that are relevant to the circuit, and creating a mutex list comprising each of the mutually exclusive signal relationships in the circuit that include at least two of the signals that are relevant to the circuit. Also in the preferred embodiment, the list of all possible permutations of active signals used in the analysis is performed by creating an active signal list, that comprises one or more active signal elements that each comprise a different permutation of the relevant signals and that also does not include any of the mutually exclusive signal relationships contained in the mutex list.
In accordance with the apparatus of the invention, an electrical rules checker for detecting violations of a set of electrical rules in a digital circuit design includes a mutex list generator which reads a mutex file containing a set of mutually exclusive signal relationships of the circuit design. The electrical rules checker also includes an active signal generator which calculates a set of active signal permutations relevant to the circuit that also do not include any of the mutually exclusive signal relationships. A test controller then causes a test to be applied to the circuit design at least once for each different active signal permutation in the set of active signal permutations.